1. Field of the Invention
The present invention relates to ferroelectric capacitors and ferroelectric memories. More particularly, the invention relates to alloy compositions for the bottom electrode of a ferroelectric capacitor, which can be used in a ferroelectric memory.
2. Background Information
Ferroelectric random access memory (FRAM) is a non-volatile memory that maintains stored data without the need for maintaining power to the device. A memory cell (also referred to as a storage node) of an FRAM commonly employs a ferroelectric capacitor having a bottom electrode, a top electrode and a ferroelectric layer disposed therebetween. The ferroelectric layer is made of a ferroelectric material that exhibits spontaneous electric polarization that can be maintained in the absence of power and that can be reversed in direction by the application of an appropriate electric field. Thus, the polarization direction of the ferroelectric layer of a given memory cell corresponds to a data storage state.
FIG. 1 illustrates a portion of memory cell 100 of an FRAM comprising a conventional three dimensional ferroelectric capacitor 101. The memory cell 100 comprises a Si substrate 110 having a source region 114 in contact with a contact plug 122. The contact plug is disposed within a first SiO2 layer 120. A TiAlN oxidation barrier 103 is disposed within a trench 111 in a second SiO2 layer 128 and in contact with the contact plug 122. A Ti adhesion layer 105 is disposed within the trench 111 and on the TiAlN oxidation barrier 103.
The ferroelectric capacitor 101 is disposed is within the trench 111 and in contact with the Ti adhesion layer 105. The ferroelectric capacitor 101 comprises an iridium (Ir) bottom electrode 102, a lead titanate (PTO) seed layer 107 disposed on the bottom and sides of the Ir bottom electrode 102, a lead-zirconate-titanate (PZT) ferroelectric layer 104 disposed adjacent to the Ir bottom electrode 102 and in contact with the PTO seed layer 107, and a top electrode 106 disposed on the PZT ferroelectric layer 104. The Ti adhesion layer 105 is conventionally used because the Ir bottom electrode 102 would not otherwise adhere well to the sidewalls of the trench 111 formed in the second SiO2 layer 128.
FIG. 2 illustrates another conventional ferroelectric capacitor 200 comprising an Ir bottom electrode 202, a PZT ferroelectric layer 204 and a top electrode 106. U.S. Patent Application Publication No. 2003/0112649 discloses a ferroelectric memory with a ferroelectric capacitor wherein the bottom electrode is an Ir layer or a Ru layer. U.S. Pat. No. 6,368,910 discloses ferroelectric memories with ferroelectric capacitors wherein the bottom electrode of the capacitor is a Pt layer, an Ir layer or a Ru layer. The entire contents of U.S. 2003/0112649 and U.S. Pat. No. 6,368,910 are incorporated herein by reference.
There is a trend to manufacture FRAM such as the FRAM 100 illustrated in FIG. 1 at smaller cell sizes and at increased memory densities (e.g., manufacturing FRAM having smaller three-dimensional capacitors such as capacitor 101). With regard to this trend, the present inventors have observed that fabrication problems or performance problems can arise because there can be insufficient space within the trench 111 to form the multiplicity of layers 102-107 at sufficient thicknesses to possess good film quality, especially with regard to the PZT ferroelectric layer 104. Thus, for a trench 111 having a diameter of about 0.15 μm and below, for example, forming the conventional multiplicity of layers 102-107 may require forming the PZT ferroelectric layer 104 at a small thickness such that the that PZT ferroelectric layer 104 suffers greater leakage current than is desired. Greater leakage current can result in greater power consumption and/or poorer retention of stored information in a corresponding FRAM. Alternatively, forming the Ti adhesion layer 105, the Ir bottom electrode 102, and the PTO seed layer 107, and the ferroelectric layer 304 at optimal thicknesses may leave too little space to form a top electrode 106 of sufficient thickness that also conforms to the PZT ferroelectric layer along its sidewalls. In other words, the opening in the trench 111 may get “plugged” during fabrication such that a conforming top electrode 106 of sufficient thickness cannot be formed. It is also possible that there may not be sufficient space to form the ferroelectric layer 304 of a desired thickness.
The present inventors have also observed that the conventional use of an Ir layer as a bottom electrode 102 can result in a rough surface of a PZT ferroelectric layer 104 deposited thereon (e.g., without a PTO seed layer 107), wherein a rougher surface of the PZT ferroelectric layer 104 is indicative of relatively poorer film quality compared to smoother PZT surfaces. The relatively poorer film quality of PZT ferroelectric layers that have rougher surfaces can lead to decreased performance of a ferroelectric capacitor in the form of greater leakage current, for example, which can result in greater power consumption and/or poorer retention of stored information in a corresponding FRAM. Thus, greater thicknesses of the ferroelectric layer 104 may be needed to achieve acceptable performance in such devices. However, as noted above, increasing the film thickness of the ferroelectric layer 104 may not be compatible with the trend of decreasing cell sizes and increasing memory densities.
In addition, in instances where it is desirable for the bottom electrode layer to comprise a conductive oxide, deposition of iridium oxide is difficult. Moreover, using Ir for the entire bottom electrode is costly due to its high cost.